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64k/128k x 9 deep sync fifo s cy7c428 1 cy7c429 1 cypress semiconductor corporation ? 3901 north first street san jose , ca 95134 408-943-2600 document #: 38-06007 rev. *b revised august 19, 2003 features ? high-speed, low-power, first-in first-out (fifo) memories 64k 9 (cy7c4281) 128k 9 (cy7c4291) 0.5-micron cmos for optimum speed/power high-speed 100-mhz operation (10-ns read/write cycle times) low power ?i cc = 40 ma ? i sb = 2 ma fully asynchronous and simultaneous read and write operation empty, full, and programmable almost empty and almost full status flags ttl compatible output enable (oe ) pin independent read and write enable pins center power and ground pins for reduced noise supports free-running 50% duty cycle clock inputs width expansion capability 32-pin plcc pin-compatible density upgrade to cy7c42x1 family pin-compatible density upgrade to idt72201/11/21/31/41/51 functional description the cy7c4281/91 are high-speed, low-power fifo memories with clocked read and write interfaces. all are nine bits wide. the cy7c4281/91 are pin-compatible to the cy7c42x1 synchronous fifo family. programmable features include almost full/almost empty flags. these fifos provide solutions for a wide variety of data buffering needs, including high-speed data acquisition, multiprocessor inter- faces, and communications buffering. these fifos have nine-bit input and output ports that are controlled by separate clock and enable signals. the input port is controlled by a free-running clock (wclk) and two write-enable pins (wen1 , wen2/ld ). when wen1 is low and wen2/ld is high, data is written into the fifo on the rising edge of the wclk signal. while wen1 , wen2/ld is held active, data is continually written into the fifo on each wclk cycle. the output port is controlled in a similar manner by a free-running read clock (rclk) and two read enable pins (ren1 , ren2 ). in addition, the cy7c4281/91 has an output enable pin (oe ). the read (rclk) and write (wclk) clocks may be tied together for single-clock operation or the two clocks may be run indepen- dently for asynchronous read/write applications. clock frequencies up to 100 mhz are achievable. depth expansion is possible using one enable input for system control, while the other enable is controlled by expansion logic to direct the flow of data. three-state output register read control flag logic write control write pointer read pointer reset logic input register flag program register d 0 ? 8 rclk q 0? 8 wen1 wclk rs oe dual port 64k x 9 128k x 9 wen2/ld ren1 ren2 ef pae paf ff ramarray l ogic block diagram pin configuration plcc d 1 d 0 rclk v cc d 8 d 7 d 6 d 5 d 4 d 3 gnd wclk wen2/ld q 8 q 7 d 2 paf pae 5 6 7 8 9 10 11 12 13 ren1 oe ren2 4321 3130 32 21 22 23 24 27 28 29 25 26 14 15 16 17 18 19 20 q 6 q 5 wen1 rs ff q 0 q 1 q 2 q 3 q 4 ef top view cy7c4281 cy7c4291
cy7c428 1 cy7c429 1 document #: 38-06007 rev. *b page 2 of 16 pin definitions signal name description i/o description d 0 ? 8 data inputs i data inputs for 9-bit bus . q 0 ? 8 data outputs o data outputs for 9-bit bus . wen1 write enable 1 i the only write enable when device is configured to have programmable flags . data is written on a low-to-high transition of wclk when wen1 is asserted and ff is high. if the fifo is configured to have two write enables, data is written on a low-to-high transition of wclk when wen1 is low and wen2/ld and ff are high. wen2/ld dual mode pin write enable 2 i if high at reset, this pin operates as a second write enable . if low at reset, this pin operates as a control to write or read the programmable flag offsets. wen1 must be low and wen2 must be high to write data into the fifo. data will not be written into the fifo if the ff is low. if the fifo is configured to have programmable flags, wen2/ld is held low to write or read the programmable flag offsets. load ren1 , ren2 read enable inputs i enables the device for read operation . both ren1 and ren2 must be asserted to allow a read operation. wclk write clock i the rising edge clocks data into the fifo when wen1 is low and wen2/ld is high and the fifo is not full . when ld is asserted, wclk writes data into the programmable flag-offset register. rclk read clock i the rising edge clocks data out of the fifo when ren1 and ren2 are low and the fifo is not empty . when wen2/ld is low, rclk reads data out of the program- mable flag-offset register. ef empty flag o when ef is low, the fifo is empty. ef is synchronized to rclk . ff full flag o when ff is low, the fifo is full. ff is synchronized to wclk . pae programmable almost empty o when pae is low, the fifo is almost empty based on the almost empty offset value programmed into the fifo . pae is synchronized to rclk. paf programmable almost full o when paf is low, the fifo is almost full based on the almost full offset value programmed into the fifo . paf is synchronized to wclk. rs reset i resets device to empty condition . a reset is required before an initial read or write operation after power-up. oe output enable i when oe is low, the fifo?s data outputs drive the bus to which they are connected . if oe is high, the fifo?s outputs are in high z (high-impedance) state. cy7c4281 cy7c4291 density 64k x 9 128k x 9 package 32-pin plcc 32-pin plcc selection guide 7c4281/91-10 7c4281/91-15 7c4281/91-25 unit maximum frequency 100 66.7 40 mhz maximum access time 8 10 15 ns minimum cycle time 10 15 25 ns minimum data or enable set-up 3 4 6 ns minimum data or enable hold 0.5 1 1 ns maximum flag delay 8 10 15 ns active power supply current (i cc1 )commercial404040ma industrial 45
cy7c428 1 cy7c429 1 document #: 38-06007 rev. *b page 3 of 16 functional description (continued) the cy7c4281/91 provides four status pins: empty, full, programmable almost empty, and programmable almost full. the almost empty/almost full flags are programmable to single-word granularity. the programmable flags default to empty+7 and full-7. the flags are synchronous, i.e., they change state relative to either the read clock (rclk) or the write clock (wclk). when entering or exiting the empty and almost empty states, the flags are updated exclusively by the rclk. the flags denoting almost full and full states are updated exclusively by wclk. the synchronous flag architecture guarantees that the flags maintain their status for at least one cycle. all configurations are fabricated using an advanced 0.5 cmos technology. input esd protection is greater than 2001v, and latch-up is prevented by the use of guard rings. architecture the cy7c4281/91 consists of an array of 64k to 128k words of nine bits each (implemented by a dual-port array of sram cells), a read pointer, a write pointer, control signals (rclk, wclk, ren1 , ren2 , wen1 , wen2, rs ), and flags (ef , pae , paf , ff ). resetting the fifo upon power-up, the fifo must be reset with a reset (rs ) cycle. this causes the fifo to enter the empty condition signified by ef being low. all data outputs (q 0?8 ) go low t rsf after the rising edge of rs . in order for the fifo to reset to its default state, the user must not read or write while rs is low. all flags are guaranteed to be valid t rsf after rs is taken low. fifo operation when the wen1 signal is active low, wen2 is active high, and ff is active high, data present on the d 0?8 pins is written into the fifo on each rising edge of the wclk signal. similarly, when the ren1 and ren2 signals are active low and ef is active high, data in the fifo memory will be presented on the q 0?8 outputs. new data will be presented on each rising edge of rclk while ren1 and ren2 are active. ren1 and ren2 must set up t ens before rclk for it to be a valid read function. wen1 and wen2 must occur t ens before wclk for it to be a valid write function. an output enable (oe ) pin is provided to three-state the q 0?8 outputs when oe is asserted. when oe is enabled (low), data in the output register will be available to the q 0?8 outputs after t oe . if devices are cascaded, the oe function will only output data on the fifo that is read enabled. the fifo contains overflow circuitry to disallow additional writes when the fifo is full, and underflow circuitry to disallow additional reads when the fifo is empty. an empty fifo maintains the data of the last valid read on its q 0?8 outputs even after additional reads occur. write enable 1 (wen1 ) ? if the fifo is configured for programmable flags, write enable 1 (wen1 ) is the only write enable control pin. in this configuration, when write enable 1 (wen1 ) is low, data can be loaded into the input register and ram array on the low-to-high transition of every write clock (wclk). data is stored is the ram array sequentially and independently of any on-going read operation. write enable 2/load (wen2/ld ) ? this is a dual-purpose pin. the fifo is configured at reset to have programmable flags or to have two write enables, which allows for depth expansion. if write enable 2/load (wen2/ld ) is set active high at reset (rs = low), this pin operates as a second write enable pin. if the fifo is configured to have two write enables, when write enable (wen1 ) is low and write enable 2/load (wen2/ld ) is high, data can be loaded into the input register and ram array on the low-to-high transition of every write clock (wclk). data is stored in the ram array sequentially and independently of any on-going read operation. programming when wen2/ld is held low during reset, this pin is the load (ld ) enable for flag offset programming. in this configuration, wen2/ld can be used to access the four nine-bit offset registers contained in the cy7c4281/4291 for writing or reading data to these registers. when the device is configured for programmable flags and both wen2/ld and wen1 are low, the first low-to-high transition of wclk writes data from the data inputs to the empty offset least significant bit (lsb) register. the second, third, and fourth low-to-high transitions of wclk store data in the empty offset most significant bit (msb) register, full offset lsb register, and full offset msb register, respectively, when wen2/ld and wen1 are low. the fifth low-to-high transition of wclk while wen2/ld and wen1 are low writes data to the empty lsb register again. figure 1 shows the registers sizes and default values for the various device types. figure 1. offset register location and default values 64k 9 8 0 8 0 8 0 empty offset (lsb) reg. default value = 007h full offset (lsb) reg default value = 007h (msb) 7 7 7 8 0 8 0 8 0 8 0 empty offset (lsb) reg. default value = 007h full offset (lsb) reg default value = 007h (msb) (msb) 7 7 128k 9 8 0 (msb) 7 default value = 000h default value = 000h default value = 000h default value = 000h
cy7c428 1 cy7c429 1 document #: 38-06007 rev. *b page 4 of 16 it is not necessary to write to all the offset registers at one time. a subset of the offset registers can be written; then by bringing the wen2/ld input high, the fifo is returned to normal read and write operation. the next time wen2/ld is brought low, a write operation stores data in the next offset register in sequence. the contents of the offset registers can be read to the data outputs when wen2/ld is low and both ren1 and ren2 are low. low-to-high transitions of rclk read register contents to the data outputs. writes and reads should not be performed simultaneously on the offset registers. programmable flag (pae, paf) operation whether the flag offset registers are programmed as described in table 1 or the default values are used, the programmable almost-empty flag (pae ) and programmable almost-full flag (paf ) states are determined by their corre- sponding offset registers and the difference between the read and write pointers. the number formed by the empty offset least significant bit register and empty offset most significant bit register is referred to as n and determines the operation of pae . paf is synchronized to the low-to-high transition of rclk by one flip-flop and is low when the fifo contains n or fewer unread words. pae is set high by the low-to-high transition of rclk when the fifo contains (n + 1) or greater unread words. the number formed by the full offset least significant bit register and full offset most significant bit register is referred to as m and determines the operation of paf . pae is synchro- nized to the low-to-high transition of wclk by one flip-flop and is set low when the number of unread words in the fifo is greater than or equal to cy7c4281 (64k-m) and cy7c4291 (128k-m). paf is set high by the low-to-high transition of wclk when the number of available memory locations is greater than m. width expansion configuration word width may be increased simply by connecting the corre- sponding input controls signals of multiple devices. a composite flag should be created for each of the end-point status flags (ef and ff ). the partial status flags (pae and paf ) can be detected from any one device. figure 2 demon- strates a 18-bit word width by using two cy7c42x1s. any word width can be attained by adding additional cy7c42x1s. when the cy7c42x1 is in a width expansion configuration, the read enable (ren2 ) control input can be grounded (see figure 2 ). in this configuration, the write enable 2/load (wen2/ld ) pin is set to low at reset so that the pin operates as a control to load and read the programmable flag offsets. flag operation the cy7c4281/91 devices provide five flag pins to indicate the condition of the fifo contents. empty, full, pae , and paf are synchronous. full flag the full flag (ff ) will go low when the device is full. write operations are inhibited whenever ff is low regardless of the state of wen1 and wen2/ld . ff is synchronized to wclk, i.e., it is exclusively updated by each rising edge of wclk. empty flag the empty flag (ef ) will go low when the device is empty. read operations are inhibited whenever ef is low, regardless of the state of ren1 and ren2 . ef is synchronized to rclk, i.e., it is exclusively updated by each rising edge of rclk. note: 1. the same selection sequence applies to reading from the registers. ren1 and ren2 are enabled and a read is performed on the low-to-high transition of rclk. table 1. writing the offset registers ld wen wclk [1] selection 00 0 1 no operation 1 0 write into fifo 1 1 no operation empty offset (lsb) empty offset (msb) full offset (lsb) full offset (msb) table 2. status flags number of words in fifo ff paf pae ef cy7c4281 cy7c4291 00 hh l l 1 to n [2] 1 to n [2] hh l h (n+1) to (65536 ? (m+1)) (n+1) to (131072 ? (m+1)) hh hh (65536 ? m) [3] to 65535 131072 ? m) [3] to 131071 hl hh 65536 131072 ll hh
cy7c428 1 cy7c429 1 document #: 38-06007 rev. *b page 5 of 16 figure 2. block diagram of 64k x 9/128k x 9 deep sync fifo memory used in a width expansion configuration notes: 2. n = empty offset (n = 7 default value). 3. m = full offset (m = 7 default value). ff ff ef ef writeclock (wclk) write enable 1(wen1 ) write enable 2/load (wen2/ld ) programmable(paf ) full flag (ff )# 1 cy7c4281/91 9 18 data in (d) reset (rs) 9 reset (rs ) read clock (rclk) read enable 1 (ren1 ) output enable (oe ) programmable(pae ) empty flag (ef ) #1 9 data out (q) 918 read enable 2 (ren2 ) cy7c4281/91 empty flag (ef ) #2 full flag (ff )# 2 read enable 2 (ren2 )
cy7c428 1 cy7c429 1 document #: 38-06007 rev. *b page 6 of 16 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ....................................... ? 65 c to +150 c ambient temperature with power applied .................................................... ? 55 c to +125 c supply voltage to ground potential .................? 0.5v to +7.0v dc voltage applied to outputs in high-z state ............................................? 0.5v to v cc + 0.5v dc input voltage ....................................... ? 0.5v to v cc + 0.5v output current into outputs (low)............................. 20 ma static discharge voltage........................................... > 2001v (per mil-std-883, method 3015) latch-up current..................................................... > 200 ma note: 4. the voltage on any input or i/o pin cannot exceed the power pin during power-up. 5. t a is the ?instant on? case temperature. 6. input signals switch from 0v to 3v with a rise/fall time of less than 3 ns, clocks and clock en ables switch at maximum freque ncy 20 mhz, while data inputs switch at 10 mhz. outputs are unloaded. icc1(typical) = (20 ma + (freq ? 20 mhz)*(0.7 ma/mhz)). 7. all inputs = v cc ? 0.2v, except wclk and rclk (which are at frequency = 0 mhz). all outputs are unloaded. 8. tested initially and after any design or process changes that may affect these parameters. 9. c l = 30 pf for all ac parameters except for t ohz . 10. c l = 5 pf for t ohz . operating range [4] range ambient temperature v cc commercial 0 c to +70 c 5v 10% industrial [5] ? 40 c to +85 c 5v 10% electrical characteristics over the operating range parameter description test conditions 7c42x1 ? 10 7c42x1 ? 15 7c42x1 ? 25 unit min. max. min. max. min. max. v oh output high voltage v cc = min., i oh = ? 2.0 ma 2.4 2.4 2.4 v v ol output low voltage v cc = min., i ol = 8.0 ma 0.4 0.4 0.4 v v ih input high voltage 2.0 v cc 2.0 v cc 2.0 v cc v v il input low voltage ? 0.5 0.8 ? 0.5 0.8 ? 0.5 0.8 v i ix input leakage current v cc = max. ? 10 +10 ? 10 +10 ? 10 +10 a i ozl i ozh output off, high z current oe > v ih , v ss < v o < v cc ? 10 +10 ? 10 +10 ? 10 +10 a i cc1 [6] active power supply current com?l 40 40 40 ma ind 45 45 45 ma i sb [7] average standby current com?l 2 2 2 ma ind 2 ma capacitance [8] parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 5.0v 5 pf c out output capacitance 7 pf ac test loads and waveforms [9, 10] 3.0v 5v output r11.1k ? r2 680 ? c l including jig and scope gnd 90% 10% 90% 10% 3ns 3 ns output 1.91v equivalent to: th venin equivalent 420 ? all input pulses
cy7c428 1 cy7c429 1 document #: 38-06007 rev. *b page 7 of 16 switching characteristics over the operating range parameter description 7c42x1-10 7c42x1-15 7c42x1-25 unit min. max. min. max. min. max. t s clock cycle frequency 100 66.7 40 mhz t a data access time 2 8 2 10 2 15 ns t clk clock cycle time 10 15 25 ns t clkh clock high time 4.5 6 10 ns t clkl clock low time 4.5 6 10 ns t ds data set-up time 3 4 6 ns t dh data hold time 0.5 1 1 ns t ens enable set-up time 3 4 6 ns t enh enable hold time 0.5 1 1 ns t rs reset pulse width [11] 10 15 25 ns t rss reset set-up time 8 10 15 ns t rsr reset recovery time 8 10 15 ns t rsf reset to flag and output time 10 15 25 ns t olz output enable to output in low z [12] 0 0 0 ns t oe output enable to output valid 3 7 3 8 3 12 ns t ohz output enable to output in high z [12] 3 7 3 8 3 12 ns t wff write clock to full flag 8 10 15 ns t ref read clock to empty flag 8 10 15 ns t paf clock to programmable almost-full flag 8 10 15 ns t pae clock to programmable almost-full flag 8 10 15 ns t skew1 skew time between read clock and write clock for empty flag and full flag 5 6 10 ns t skew2 skew time between read clock and write clock for almost-empty flag and almost-full flag 10 15 18 ns notes: 11. pulse widths less than minimum values are not allowed. 12. values guaranteed by design, not currently tested.
cy7c428 1 cy7c429 1 document #: 38-06007 rev. *b page 8 of 16 switching waveforms notes: 13. t skew1 is the minimum time between a rising rclk edge and a rising wclk edge to guarantee that ff will go high during the current clock cycle. if the time between the rising edge of rclk and the rising edge of wclk is less than t skew1 , then ff may not change state until the next wclk rising edge. 14. t skew1 is the minimum time between a rising wclk edge and a rising rclk edge to guarantee that ef will go high during the current clock cycle. it the time between the rising edge of wclk and the rising edge of rclk is less than t skew2 , then ef may not change state until the next rclk rising edge. write cycle timing t clkh t clkl no operation t ds t skew1 t ens wen1 t clk t dh t wff t wff t enh wclk d 0 ?d 17 ff ren1 , ren2 rclk no operation wen2 (if applicable) [ 13 ] ren1 , ren2 read cycle timing t clkh t clkl no operation t skew1 wen1 t ckl t ohz t ref t ref rclk q 0 ?q 17 ef wclk oe t oe t ens t olz t a t enh valid data wen2 [ 14 ]
cy7c428 1 cy7c429 1 document #: 38-06007 rev. *b page 9 of 16 notes: 15. the clocks (rclk, wclk) can be free-running during reset. 16. after reset, the outputs will be low if oe = 0 and three-state if oe =1. 17. holding wen2/ld high during reset will make the pin act as a second enable pin. holding wen2/ld low during reset will make the pin act as a load enable for the programmable flag offset registers. switching waveforms (continued) reset timing t rs t rsr q 0- q 8 rs t rsf t rsf t rsf o e =1 oe=0 ren1 , ren2 ef ,pae ff , paf t rss t rsr t rss t rsr t rss w en2/ld wen1 [ 15 ] [ 17 ] [ 16 ]
cy7c428 1 cy7c429 1 document #: 38-06007 rev. *b page 10 of 16 notes: 18. when t skew1 > minimum specification, t frl (maximum) = t clk + t skew2 . when t skew1 < minimum specification, t frl (maximum) = either 2*t clk + t skew1 or t clk + t skew1 . the latency timing applies only at the empty boundary (ef = low). 19. the first word is available the cycle after ef goes high, always. switching waveforms (continued) d 0 (first valid write) first data word latency after reset with read and write t skew1 wen1 wclk q 0 ?q 8 ef ren1 , ren2 oe t oe t ens t olz t ds rclk t ref t a t frl d 1 d 2 d 3 d 4 d 0 d 1 d 0 ?d 8 t a wen2 (if applicable) [ 18 ] [ 19 ]
cy7c428 1 cy7c429 1 document #: 38-06007 rev. *b page 11 of 16 switching waveforms (continued) data write 2 data write 1 t skew1 data in output register empty flag timing wclk q 0 ?q 8 ef ren1 , ren2 oe t ds rclk t ref t a t frl d 0 ?d 8 data read t skew2 t frl t ref t ds wen2 (if applicable) ens t ref low [ 18 ] [ 18 ] t ens wen1 t enh t ens t enh t ens t enh t t enh
cy7c428 1 cy7c429 1 document #: 38-06007 rev. *b page 12 of 16 notes: 20. t skew2 is the minimum time between a rising wclk and a rising rclk edge for pae to change state during that clock cycle. if the time between the edge of wclk and the rising rclk is less than t skew2 , then pae may not change state until the next rclk. 21. pae offset = n. 22. if a read is preformed on this rising edge of the read clock, there will be empty + (n ? 1) words in the fifo when pae goes low. switching waveforms (continued) q 0 ?q 8 ren1 , ren2 wen1 wen2 (if applicable) d 0 ?d 8 next data read data write no write data in output register full flag timing ff wclk oe rclk t a data read t skew1 t ds t ens t enh t wff t a t skew1 t ens t enh t wff data write no write t wff low [ 13 ] [ 13 ] t enh programmable almost empty flag timing wclk pae rclk t clkh t ens t clkl t ens t pae n + 1 words in fifo t enh t ens t enh t ens t pae ren1 , ren2 wen1 wen2 (if applicable) t skew2 [ 20 ] note 21 note 22
cy7c428 1 cy7c429 1 document #: 38-06007 rev. *b page 13 of 16 notes: 23. if a write is performed on this rising edge of the write clock, there will be full ? (m ? 1) words of the fifo when paf goes low. 24. paf offset = m. 25. 16,384 ? m words for cy7c4281, 32,768 ? m words for cy4291. 26. t skew2 is the minimum time between a rising rclk edge and a rising wclk edge for paf to change during that clock cycle. if the time between the rising edge of rclk and the rising edge of wclk is less than t skew2 , then paf may not change state until the next wclk. switching waveforms (continued) t enh programmable almost full flag timing wclk paf rclk t clkh t ens (full ? m) words in fifo t clkl t ens full ? (m+1)words in fifo t enh t ens t enh t ens t paf ren1, ren2 wen1 wen2 (if applicable) t skew2 t paf [ 25 ] [ 26 ] [23] note 24 t enh write programmable registers wen2/ld wclk t clkh t ens t clkl pae offset lsb d 0 ?d 8 wen1 t ens paf offset msb t clk t ds t dh pae offset msb paf offset lsb
cy7c428 1 cy7c429 1 document #: 38-06007 rev. *b page 14 of 16 switching waveforms (continued) paf offset msb paf offset lsb t enh r ead programmable registers wen2/ld rclk t clkh t ens t clkl pae offset lsb q 0 ?q 15 ren1, ren2 t ens pae offset msb t clk unknown t a ordering information 64k x 9 deep sync fifo speed (ns) ordering code package name package type operating range 10 cy7c4281-10jc j65 32-lead plastic leaded chip carrier commercial cy7c4281-10ji j65 32-lead plastic leaded chip carrier industrial 15 cy7c4281-15jc j65 32-lead plastic leaded chip carrier commercial 25 cy7c4281-25jc j65 32-lead plastic leaded chip carrier commercial 128k x 9 deep sync fifo speed (ns) ordering code package name package type operating range 10 cy7c4291-10jc j65 32-lead plastic leaded chip carrier commercial cy7c4291-10ji j65 32-lead plastic leaded chip carrier industrial 15 cy7c4291-15jc j65 32-lead plastic leaded chip carrier commercial 25 CY7C4291-25JC j65 32-lead plastic leaded chip carrier commercial
cy7c428 1 cy7c429 1 document #: 38-06007 rev. *b page 15 of 16 ? cypress semiconductor corporation, 2003. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semi conductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support syst ems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies th at the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. package diagrams all product and company names mentioned in this document are the trademarks of their respective holders. 32-lead plastic leaded chip carrier j65 51-85002- * b
cy7c428 1 cy7c429 1 document #: 38-06007 rev. *b page 16 of 16 document history page document title: cy7c4281, cy7c4291 64k/128k x 9 deep sync fifos document number: 38-06007 rev. ecn no. issue date orig. of change description of change ** 106468 07/12/01 szv change from spec number: 38-00587 to 38-06007 *a 122259 12/26/02 rbi power up requirements added to operating range information *b 127854 08/22/03 fsg removed preliminary fixed empty flag timing diagram switching waveform diagram typo fixed

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